Digital Design I ? EE2369, Fall 2003, UTEP,
Verilog HDL- discuss lab 3. 16-Jun. Verilog HDL - Static Timing Analysis with
Synopsys PrimeTIme. 17-Jun. revista por examen 1 - asynch clock boundaries.
18-Jun. Lab 3 - State Machine. 22-Jun. Examen 1. 23-Jun. Design for Test. 24-
Jun. Fault Modeling. 25-Jun. Lab 4 - Reflex tester workshop. 29-Jun. Fault
Simulation.