Examen de control - digsys.upc.edu
VERY IMPORTANT: Draw a general schematic or plan, develop the exercise and
justify the results always explaining what are you doing. Minimum 1[1]: Designing
an 6-bit comparator using VHDL. Develop the VHDL code for the comparator
COMP8 sketched in Fig. 1a using an internal architecture consisting in
cascadable ...