TD SYNTHESE VHDL

1er exercice: Générateur monocoup. Soit le programme VHDL ci-dessous:.
library IEEE;. use IEEE.STD_LOGIC_1164.ALL;. use IEEE.STD_LOGIC_ARITH.
ALL;.

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TD Graphes d'états Synthèse 1er exercice: Générateur monocoup
Soit le programme VHDL ci-dessous:. library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; entity monocoup is
Port ( horloge : in std_logic;
h_1hz : in std_logic;
y1 : out std_logic;
y2 : out std_logic);
end monocoup; architecture Behavioral of monocoup is
signal etat : std_logic_vector(1 downto 0);
begin
process (horloge)
begin
if (horloge'event and horloge='1') then
case etat is
when "00" =>
if (h_1hz = '0' )then etat
if (h_1hz = '1' )then etat etatetat